Uusi opinto-opas (sisältäen myös opetusohjelmat) lukuvuodelle 2018-2019 sijaitsee osoitteessa https://opas.peppi.utu.fi . Tältä sivustolta löytyvät enää vanhat opinto-oppaat ja opetusohjelmat.

The new study guide (incl. teaching schedules) for academic year 2018-2019 can be found at https://studyguide.utu.fi. This site contains only previous years' guides.

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Archived Curricula Guide 2013–2014
Curricula Guide is archieved. Please refer to current Curricula Guides
ETT_2061 System Verification 5 ECTS
Organised by
Electronics and Communication Technology

Learning outcomes

To learn the principles of verification methods for modern parallel systems, the course guides a student through the principles of building reusable verification environment and formal model checking.

Contents

The course commences by introducing shortly a system-level object-oriented modelling and verification language SystemVerilog. Then the course delves into the Universal Verification Methodology (UVM) and shows how to create a reusable verification environment using UVM. In the final phase, the course focuses on motivation of formal verification and model checking of parallel systems using linear temporal logic (LTL) in the PROMELA/SPIN framework.

Modes of study

Option 1
Available for:
  • Degree Programme Students
  • Other Students
  • Doctoral Students
  • Exchange Students
Written exam
  • In English
Exercise(s)
  • In English
English:
Written exam and Exercise(s)

Evaluation

Numeric 0-5.

Belongs to following study modules

Department of Future Technologies
Department of Future Technologies
2013–2014
Teaching
Archived Teaching Schedule. Please refer to current Teaching Shedule.
Department of Future Technologies
DP in Computer Science
DP in Electr. and Communication Technology
Finnish Study Modules