Uusi opinto-opas (sisältäen myös opetusohjelmat) lukuvuodelle 2018-2019 sijaitsee osoitteessa https://opas.peppi.utu.fi . Tältä sivustolta löytyvät enää vanhat opinto-oppaat ja opetusohjelmat.

The new study guide (incl. teaching schedules) for academic year 2018-2019 can be found at https://studyguide.utu.fi. This site contains only previous years' guides.

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Arkistoitu opetussuunnitelma 2013–2014
Selaamasi opetussuunnitelma ei ole enää voimassa. Tarkista tiedot voimassa olevasta opetussuunnitelmasta.
ETT_2061 System Verification 5 op
Organised by
Electronics and Communication Technology

Learning outcomes

To learn the principles of verification methods for modern parallel systems, the course guides a student through the principles of building reusable verification environment and formal model checking.


The course commences by introducing shortly a system-level object-oriented modelling and verification language SystemVerilog. Then the course delves into the Universal Verification Methodology (UVM) and shows how to create a reusable verification environment using UVM. In the final phase, the course focuses on motivation of formal verification and model checking of parallel systems using linear temporal logic (LTL) in the PROMELA/SPIN framework.

Modes of study

Option 1
Available for:
  • Degree Programme Students
  • Other Students
  • Doctoral Students
  • Exchange Students
Written exam
  • In English
  • In English
Written exam and Exercise(s)


Numeric 0-5.

Belongs to following study modules

Tulevaisuuden teknologioiden laitos
Tulevaisuuden teknologioiden laitos
Archived Teaching Schedule. Please refer to current Teaching Shedule.
Tulevaisuuden teknologioiden laitos