Uusi opinto-opas (sisältäen myös opetusohjelmat) lukuvuodelle 2018-2019 sijaitsee osoitteessa https://opas.peppi.utu.fi . Tältä sivustolta löytyvät enää vanhat opinto-oppaat ja opetusohjelmat.

The new study guide (incl. teaching schedules) for academic year 2018-2019 can be found at https://studyguide.utu.fi. This site contains only previous years' guides.

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Arkistoitu opetussuunnitelma 2013–2014
Selaamasi opetussuunnitelma ei ole enää voimassa. Tarkista tiedot voimassa olevasta opetussuunnitelmasta.
DTEK8067 HDL Based Design 5 op
Organised by
Information and Communication Technology

Learning outcomes

To learn how to design digital systems with hardware description languages (HDLs), especially VHDL to get hands on experience on design flow for modern electronic systems. Is able to used modern CAD tools for simulation and synthesis for performance and trade-off studies towards implementation. Understands synthesis and simulation constraints including timing closures as well as power and area constraints


VHDL syntax and coding styles. Modeling combinational and sequential components as well as data paths and control systems. Design flow. Simulation as a verification method and the creation of testbenches for simulations. Synthesizable VHDL, synthesis process and constraining for synthesis. The usage of modern CAD tools for simulation and synthesis. Introduction to Verilog.

Modes of study

Option 1
Available for:
  • Degree Programme Students
  • Other Students
  • Doctoral Students
  • Exchange Students
  • In English
Written exam
  • In English
Exercise(s) and Written exam



Belongs to following study modules

Tulevaisuuden teknologioiden laitos
Tulevaisuuden teknologioiden laitos
Tulevaisuuden teknologioiden laitos
Archived Teaching Schedule. Please refer to current Teaching Shedule.
Tulevaisuuden teknologioiden laitos