DTEK8067 HDL Based Design 5 ECTS
Organised by
Information and Communication Technology

Learning outcomes

To learn how to design digital systems with hardware description languages (HDLs), especially VHDL to get hands on experience on design flow for modern electronic systems. Is able to used modern CAD tools for simulation and synthesis for performance and trade-off studies towards implementation. Understands synthesis and simulation constraints including timing closures as well as power and area constraints

Contents

VHDL syntax and coding styles. Modeling combinational and sequential components as well as data paths and control systems. Design flow. Simulation as a verification method and the creation of testbenches for simulations. Synthesizable VHDL, synthesis process and constraining for synthesis. The usage of modern CAD tools for simulation and synthesis. Introduction to Verilog.

Modes of study

Option 1
Available for:
  • Degree Programme Students
  • Other Students
  • Doctoral Students
  • Exchange Students
Exercise(s)
  • In English
Written exam
  • In English

Evaluation

Pass/fail.

Belongs to following study modules

Department of Future Technologies
EC1
Department of Future Technologies
2016–2017
Teaching
Archived Teaching Schedule. Please refer to current Teaching Shedule.
Department of Future Technologies
DP in Computer Science
DP in Computer Science
DP Bachelor of Science in Techn.(Communication St)
DP in Information and Communication Technology
MDP in Digital Health and Life Sciences (Tech.)
Finnish Study Modules