ETT_2061 System Verification 5 op
Organised by
Electronics and Communication Technology

Learning outcomes

Students will be able to identify the critical functions of a digital hardware system. Students will be able to create a verification plan to verify the identified critical functions. Students will be able to employ a verification methodology to implement the verification plan. Students will be able to verify the functionality of digital hardware systems using the implemented verification environment.

Contents

The course guides a student through the principles of building reusable verification environment. The course commences by introducing shortly a system-level object-oriented modelling and verification language SystemVerilog, after which the course delves into the Universal Verification Methodology (UVM) and shows how to create a reusable verification environment using UVM.

Modes of study

Option 1
Available for:
  • Degree Programme Students
  • Other Students
  • Doctoral Students
  • Exchange Students
Written exam
  • In English
Exercise(s)
  • In English

Evaluation

Numeric 0-5.

Belongs to following study modules

Tulevaisuuden teknologioiden laitos
EC1
Tulevaisuuden teknologioiden laitos
Tulevaisuuden teknologioiden laitos
2016–2017
Teaching
Archived Teaching Schedule. Please refer to current Teaching Shedule.
Tulevaisuuden teknologioiden laitos
MDP in Bioinformatics
MDP in Embedded Computing
MDP in Digital Health and Life Sciences (Tech.)
Opintokokonaisuudet